This invention relates to serial data receivers. More particularly, this invention relates to apparatus for controlling byte alignment in deserialized data output of a serial data receiver, especially a serial data receiver used with a programmable logic device.
High-speed serial signaling is becoming an increasingly important form of signaling between electronic devices. For example, Low Voltage Differential Signaling (xe2x80x9cLVDSxe2x80x9d) has become a common form of signaling. Typically the data represent bytes of information that are being transmitted one after another. The usual definition of a byte is eight bits, but as used herein xe2x80x9cbytexe2x80x9d can refer to any plural number of bits such as eight bits, nine bits, ten bits, eleven bits, or fewer or more than these numbers of bits. When the data is received, one task that the receiving circuitry must typically perform is to find the boundaries between the successive bytes in the received serial bit stream. This may be referred to as xe2x80x9cbyte alignmentxe2x80x9d or xe2x80x9cbyte synchronizationxe2x80x9d.
To facilitate byte alignment, it is typical to transmit special bytes at the start of a packet of bytes of data. The receiver circuitry looks for the special byte pattern in the incoming data. When the receiver circuitry finds the special byte pattern, it knows where the boundaries between subsequent bytes are. This makes it possible for the receiver circuitry to properly handle the subsequent bytes of data.
A problem that can occur with known byte alignment circuitry is the following. It is difficult or impossible for such circuitry, once aligned, to properly deal with subsequent receipt of the special byte pattern, especially if that pattern is received out of alignment with what has already been determined to be proper byte alignment. Such an out-of-alignment special byte pattern may be due to such circumstances as: (1) the special byte pattern originally received is not really a special byte, but just some bits in one data byte followed by some bits in the succeeding data byte that together happen to have the same pattern as a special byte; or (2) byte alignment has been lost, and byte alignment should be re-established based on the newly received special bytes.
Programmable logic devices (xe2x80x9cPLDsxe2x80x9d) are well known as shown, for example, by such references as Cliff et al. U.S. Pat. No. 5,689,195, Cliff et al. U.S. Pat. No. 5,909,126, Jefferson et al. U.S. Pat. No. 6,215,326, and Ngai et al. U.S. Pat. No. 6,407,576. In general, a PLD is a general-purpose integrated circuit device that is programmable to perform any of a wide range of logic tasks. Rather than having to design and build separate logic circuits for performing different logic tasks, general-purpose PLDs can be programmed in various different ways to perform those various logic tasks. Many manufacturers of electronic circuitry and systems find PLDs to be an advantageous way to provide various components of what they need to produce.
It is known to use high-speed serial signaling with PLDS. PLDs designed for use with high-speed serial signaling typically include, in their input/output circuitry, programmable interfaces that can be used with one or more high-speed serial protocols, with the ability to programmably select the portions of the circuitry for a particular protocol. However, although programmable, such interfaces have heretofore been built with particular choices of protocol in mind, so that even minor changes in a protocol necessitate redesigning the receiver circuitry and hence the PLD. For example, if the aforementioned byte alignment circuitry is built to recognize a particular special byte, and it is desired to use a new special byte, it may be necessary to redesign the byte alignment circuitry of the receiver, and therefore the entire receiver and by extension the entire PLD. Similarly, if other parameters change, or if improved logic for recognizing and handling byte misalignment situations is developed, new byte alignment circuitry might have to be designed.
It also is known to control byte alignment using programmable logic in the programmable core of a PLD, but heretofore this alignment has been performed on the high-speed serial data across all channels. As serial interface speeds become ever higher, accurately byte-aligning data becomes more difficult, because it becomes more difficult to assure that the bit-slipping signal arrives at the correct clock cycle. Moreover, differences in skew across different channels mean that a proper byte alignment for one channel might not be proper for all channels. If the byte alignment is not correct, further byte alignment will have to be performed before the high-speed serial interface is properly synchronized.
It would be desirable to be able to use the programmable nature of PLDs to avoid having to design and build a new high-speed serial receiver every time one parameter of a protocol changes, and to byte-align the incoming data as accurately as possible.
In accordance with this invention, a programmable logic device is provided with high-speed serial interface receiver circuitry for receiving and deserializing a plurality of channels of high-speed serial data. However, the receiver circuitry does not include complete byte alignment circuitry. Instead, each channel of the receiver circuitry is provided with bit-slipping circuitry for performing byte alignment, so that each channel can be separately aligned, taking into account the particular skew in that channel. Moreover, the byte alignment logic that controls the bit-slipping process is implemented in the PLD logic core. This allows the user to determine how the byte alignment is to be performed.
In most cases, the user would likely implement a known logic module for performing byte alignment, but by implementing such logic in the PLD logic core, the user could more easily change the special pattern that signals the beginning of a byte, or other parameters of the byte alignment process. Instead of redesigning the byte alignment circuitry in the receiver to change those parameters, the user merely reprograms the byte alignment logic in the PLD core. Similarly, the user could change the logic itself, if in a particular user application different logic for recognizing byte alignment or handling byte misalignment situations is required. The logic core of a PLD is particularly suited for designing and implementing such logic, either as conventional programmable logic or as a state machine. On the other hand, the logic core of a PLD is less well suited for performing the actual alignment process, and therefore according to the invention specialized bit-slipping circuitry for performing the alignment process continues to be provided in the high-speed serial interface circuitry.
In one embodiment, a byte boundary may be assumed initially. As the byte alignment logic in the PLD logic core monitors the incoming signal on each channel, it may determine that the initial boundary selected on a particular channel is incorrect. The logic would then send a control signal to the bit-slipping circuitry in that channel of the high-speed serial interface, instructing that circuitry to move the boundary. In one variation of this embodiment, byte alignment logic in the PLD logic core is capable of determining, in one step, the number of bits by which the boundary is misaligned, and instructs the bit-slipping circuitry to make the correct adjustment in one step. In another variation, the bit-slipping circuitry moves the boundary by one bit in response to a determination of byte misalignment. If more than one bit of slippage is required, the byte alignment logic in the PLD core will determine that the byte alignment is still incorrect, and will send another bit-slipping signal to the bit-slipping circuitry. This will continue iteratively until the boundary has been moved the correct number of bits to achieve proper alignment.
In any case, the byte alignment as just described preferably occurs in the byte domainxe2x80x94i.e., at the slower byte clock rate. This makes the byte alignment more accurate and reliable, because at slower clock rates, it is easier to account for skew between the bit-slipping signal and the data signal, so that it is easier to assure that the correct bit position is being selected as the byte boundary location.